---------------------------------------------------------------- | | | | | Zilog | | | | ZZZZZZZ 88888 000 | | Z 8 8 0 0 | | Z 8 8 0 0 0 | | Z 88888 0 0 0 | | Z 8 8 0 0 0 | | Z 8 8 0 0 | | ZZZZZZZ 88888 000 | | | | Z80 MICROPROCESSOR Instruction Set Summary | | | | | |Written by Jonathan Bowen | | Programming Research Group | | Oxford University Computing Laboratory | | 8-11 Keble Road | | Oxford OX1 3QD | | England | | | | Tel +44-865-273840 | | | |Created August 1981 | |Updated April 1985 | |Modified by Robert Taylor on 27/12/95 for compatibilty | | with TASM | |Issue 1.3 Copyright (C) J.P.Bowen 1985| ---------------------------------------------------------------- ---------------------------------------------------------------- |Mnemonic |SZHPNC|Description |Notes | |----------+------+---------------------+----------------------| |ADC A,s |***V0*|Add with Carry |A=A+s+CY | |ADC HL,ss |**?V0*|Add with Carry |HL=HL+ss+CY | |ADD A,s |***V0*|Add |A=A+s | |ADD HL,ss |--?-0*|Add |HL=HL+ss | |ADD IX,pp |--?-0*|Add |IX=IX+pp | |ADD IY,rr |--?-0*|Add |IY=IY+rr | |AND s |***P00|Logical AND |A=A&s | |BIT b,m |?*1?0-|Test Bit |m&{2^b} | |CALL cc,nn|------|Conditional Call |If cc CALL | |CALL nn |------|Unconditional Call |-(SP)=PC,PC=nn | |CCF |--?-0*|Complement Carry Flag|CY=~CY | |CP s |***V1*|Compare |A-s | |CPD |****1-|Compare and Decrement|A-(HL),HL=HL-1,BC=BC-1| |CPDR |****1-|Compare, Dec., Repeat|CPD till A=(HL)or BC=0| |CPI |****1-|Compare and Increment|A-(HL),HL=HL+1,BC=BC-1| |CPIR |****1-|Compare, Inc., Repeat|CPI till A=(HL)or BC=0| |CPL |--1-1-|Complement |A=~A | |DAA |***P-*|Decimal Adjust Acc. |A=BCD format | |DEC s |***V1-|Decrement |s=s-1 | |DEC xx |------|Decrement |xx=xx-1 | |DEC ss |------|Decrement |ss=ss-1 | |DI |------|Disable Interrupts | | |DJNZ e |------|Dec., Jump Non-Zero |B=B-1 till B=0 | |EI |------|Enable Interrupts | | |EX (SP),HL|------|Exchange |(SP)<->HL | |EX (SP),xx|------|Exchange |(SP)<->xx | |EX AF,AF' |------|Exchange |AF<->AF' | |EX DE,HL |------|Exchange |DE<->HL | |EXX |------|Exchange |qq<->qq' (except AF)| |HALT |------|Halt | | |IM n |------|Interrupt Mode | (n=0,1,2)| |IN A,(n) |------|Input |A=(n) | |IN r,(C) |***P0-|Input |r=(C) | |INC r |***V0-|Increment |r=r+1 | |INC (HL) |***V0-|Increment |(HL)=(HL)+1 | |INC xx |------|Increment |xx=xx+1 | |INC (xx+d)|***V0-|Increment |(xx+d)=(xx+d)+1 | |INC ss |------|Increment |ss=ss+1 | |IND |?*??1-|Input and Decrement |(HL)=(C),HL=HL-1,B=B-1| |INDR |?1??1-|Input, Dec., Repeat |IND till B=0 | |INI |?*??1-|Input and Increment |(HL)=(C),HL=HL+1,B=B-1| |INIR |?1??1-|Input, Inc., Repeat |INI till B=0 | |JP (HL) |------|Unconditional Jump |PC=(HL) | |JP (xx) |------|Unconditional Jump |PC=(xx) | |JP nn |------|Unconditional Jump |PC=nn | |JP cc,nn |------|Conditional Jump |If cc JP | |JR e |------|Unconditional Jump |PC=PC+e | |JR cc,e |------|Conditional Jump |If cc JR(cc=C,NC,NZ,Z)| |LD dst,src|------|Load |dst=src | |LD A,i |**0*0-|Load |A=i (i=I,R)| |LDD |--0*0-|Load and Decrement |(DE)=(HL),HL=HL-1,# | |LDDR |--000-|Load, Dec., Repeat |LDD till BC=0 | |LDI |--0*0-|Load and Increment |(DE)=(HL),HL=HL+1,# | |LDIR |--000-|Load, Inc., Repeat |LDI till BC=0 | |NEG |***V1*|Negate |A=-A | |NOP |------|No Operation | | |OR s |***P00|Logical inclusive OR |A=Avs | |OTDR |?1??1-|Output, Dec., Repeat |OUTD till B=0 | |OTIR |?1??1-|Output, Inc., Repeat |OUTI till B=0 | |OUT (C),r |------|Output |(C)=r | |OUT (n),A |------|Output |(n)=A | |OUTD |?*??1-|Output and Decrement |(C)=(HL),HL=HL-1,B=B-1| |OUTI |?*??1-|Output and Increment |(C)=(HL),HL=HL+1,B=B-1| |POP xx |------|Pop |xx=(SP)+ | |POP qq |------|Pop |qq=(SP)+ | |PUSH xx |------|Push |-(SP)=xx | |PUSH qq |------|Push |-(SP)=qq | |RES b,m |------|Reset bit |m=m&{~2^b} | |RET |------|Return |PC=(SP)+ | |RET cc |------|Conditional Return |If cc RET | |RETI |------|Return from Interrupt|PC=(SP)+ | |RETN |------|Return from NMI |PC=(SP)+ | |RL m |**0P0*|Rotate Left |m={CY,m}<- | |RLA |--0-0*|Rotate Left Acc. |A={CY,A}<- | |RLC m |**0P0*|Rotate Left Circular |m=m<- | |RLCA |--0-0*|Rotate Left Circular |A=A<- | ---------------------------------------------------------------- ---------------------------------------------------------------- |Mnemonic |SZHPNC|Description |Notes | |----------+------+---------------------+----------------------| |RLD |**0P0-|Rotate Left 4 bits |{A,(HL)}={A,(HL)}<- ##| |RR m |**0P0*|Rotate Right |m=->{CY,m} | |RRA |--0-0*|Rotate Right Acc. |A=->{CY,A} | |RRC m |**0P0*|Rotate Right Circular|m=->m | |RRCA |--0-0*|Rotate Right Circular|A=->A | |RRD |**0P0-|Rotate Right 4 bits |{A,(HL)}=->{A,(HL)} ##| |RST p |------|Restart | (p=0H,8H,10H,...,38H)| |SBC A,s |***V1*|Subtract with Carry |A=A-s-CY | |SBC HL,ss |**?V1*|Subtract with Carry |HL=HL-ss-CY | |SCF |--0-01|Set Carry Flag |CY=1 | |SET b,m |------|Set bit |m=mv{2^b} | |SLA m |**0P0*|Shift Left Arithmetic|m=m*2 | |SRA m |**0P0*|Shift Right Arith. |m=m/2 | |SRL m |**0P0*|Shift Right Logical |m=->{0,m,CY} | |SUB s |***V1*|Subtract |A=A-s | |XOR s |***P00|Logical Exclusive OR |A=Axs | |----------+------+--------------------------------------------| | F |-*01? |Flag unaffected/affected/reset/set/unknown | | S |S |Sign flag (Bit 7) | | Z | Z |Zero flag (Bit 6) | | HC | H |Half Carry flag (Bit 4) | | P/V | P |Parity/Overflow flag (Bit 2, V=overflow) | | N | N |Add/Subtract flag (Bit 1) | | CY | C|Carry flag (Bit 0) | |-----------------+--------------------------------------------| | n |Immediate addressing | | nn |Immediate extended addressing | | e |Relative addressing (PC=PC+2+offset) | | (nn) |Extended addressing | | (xx+d) |Indexed addressing | | r |Register addressing | | (rr) |Register indirect addressing | | |Implied addressing | | b |Bit addressing | | p |Modified page zero addressing (see RST) | |-----------------+--------------------------------------------| |DEFB n(,...) |Define Byte(s) | |DEFB 'str'(,...) |Define Byte ASCII string(s) | |DEFS nn |Define Storage Block | |DEFW nn(,...) |Define Word(s) | |-----------------+--------------------------------------------| | A B C D E |Registers (8-bit) | | AF BC DE HL |Register pairs (16-bit) | | F |Flag register (8-bit) | | I |Interrupt page address register (8-bit) | | IX IY |Index registers (16-bit) | | PC |Program Counter register (16-bit) | | R |Memory Refresh register | | SP |Stack Pointer register (16-bit) | |-----------------+--------------------------------------------| | b |One bit (0 to 7) | | cc |Condition (C,M,NC,NZ,P,PE,PO,Z) | | d |One-byte expression (-128 to +127) | | dst |Destination s, ss, (BC), (DE), (HL), (nn) | | e |One-byte expression (-126 to +129) | | m |Any register r, (HL) or (xx+d) | | n |One-byte expression (0 to 255) | | nn |Two-byte expression (0 to 65535) | | pp |Register pair BC, DE, IX or SP | | qq |Register pair AF, BC, DE or HL | | qq' |Alternative register pair AF, BC, DE or HL | | r |Register A, B, C, D, E, H or L | | rr |Register pair BC, DE, IY or SP | | s |Any register r, value n, (HL) or (xx+d) | | src |Source s, ss, (BC), (DE), (HL), nn, (nn) | | ss |Register pair BC, DE, HL or SP | | xx |Index register IX or IY | |-----------------+--------------------------------------------| | + - * / ^ |Add/subtract/multiply/divide/exponent | | & ~ v x |Logical AND/NOT/inclusive OR/exclusive OR | | <- -> |Rotate left/right | | ( ) |Indirect addressing | | ( )+ -( ) |Indirect addressing auto-increment/decrement| | { } |Combination of operands | | # |Also BC=BC-1,DE=DE-1 | | ## |Only lower 4 bits of accumulator A used | ---------------------------------------------------------------- Z80 Instruction Set Summary version 2000c Mnemonic Time Size CNPHZS OP-Code ========------====-====-======--=======-------- ADC A,(HL) 7 1 +0V+++ 8E ADC A,(IX+N) 19 3 +0V+++ DD 8E XX ADC A,(IY+N) 19 3 +0V+++ FD 8E XX ADC A,r 4 1 +0V+++ 88+r ADC A,HX 2 +0V+++ DD 8C ADC A,HY 2 +0V+++ FD 8C ADC A,LX 2 +0V+++ DD 8D ADC A,LY 2 +0V+++ FD 8D ADC A,N 7 2 +0V+++ CE XX ADC HL,BC 15 2 +0V ++ ED 4A ADC HL,DE 15 2 +0V ++ ED 5A ADC HL,HL 15 2 +0V ++ ED 6A ADC HL,SP 15 2 +0V ++ ED 7A ADD A,(HL) 7 1 +0V+++ 86 ADD A,(IX+N) 19 3 +0V+++ DD 86 XX ADD A,(IY+N) 19 3 +0V+++ FD 86 XX ADD A,r 4 1 +0V+++ 8r ADD A,HX 2 +0V+++ DD 84 ADD A,HY 2 +0V+++ FD 84 ADD A,LX 2 +0V+++ DD 85 ADD A,LY 2 +0V+++ FD 85 ADD A,N 7 2 +0V+++ C6 XX ADD HL,BC 11 1 +0- -- 09 ADD HL,DE 11 1 +0- -- 19 ADD HL,HL 11 1 +0- -- 29 ADD HL,SP 11 1 +0- -- 39 ADD IX,BC 15 2 +0- -- DD 09 ADD IX,DE 15 2 +0- -- DD 19 ADD IX,IX 15 2 +0- -- DD 29 ADD IX,SP 15 2 +0- -- DD 39 ADD IY,BC 15 2 +0- -- FD 09 ADD IY,DE 15 2 +0- -- FD 19 ADD IY,IY 15 2 +0- -- FD 29 ADD IY,SP 15 2 +0- -- FD 39 AND (HL) 7 1 00P1++ A6 AND (IX+N) 19 3 00P1++ DD A6 XX AND (IY+N) 19 3 00P1++ FD A6 XX AND r 4 1 00P1++ Ar AND HX 2 00P1++ DD A4 AND HY 2 00P1++ FD A4 AND LX 2 00P1++ DD A5 AND LY 2 00P1++ FD A5 AND N 7 2 00P1++ E6 XX BIT b,(HL) 12 2 -0 1+ CB 46+8*b BIT b,(IX+N) 20 4 -0 1+ DD CB XX 46+8*b BIT b,(IY+N) 20 4 -0 1+ FD CB XX 46+8*b BIT b,r 8 2 -0 1+ CB 4r+8*b CALL C,NN 17/10 3 ------ DC XX XX CALL M,NN 17/10 3 ------ FC XX XX CALL NC,NN 17/10 3 ------ D4 XX XX CALL NC,NN 17/10 3 ------ D4 XX XX CALL NN 17 3 ------ CD XX XX CALL NZ,NN 17/10 3 ------ C4 XX XX CALL P,NN 17/10 3 ------ F4 XX XX CALL PE,NN 17/10 3 ------ EC XX XX CALL PO,NN 17/10 3 ------ E4 XX XX CALL Z,NN 17/10 3 ------ CC XX XX CCF 4 1 +0- -- 3F CP (HL) 7 1 +1V+++ BE CP (IX+N) 19 3 +1V+++ DD BE XX CP (IY+N) 19 3 +1V+++ FD BE XX CP r 4 1 +1V+++ B8+r CP HX 2 +1V+++ DD BC CP HY 2 +1V+++ FD BC CP LX 2 +1V+++ DD BD CP LY 2 +1V+++ FD BD CP N 7 2 +1V+++ FE XX CPD 16 2 -1++++ ED A9 CPDR 21/16 2 -1++++ ED B9 CPI 16 2 -1++++ ED A1 CPIR 21/16 2 -1++++ ED B1 CPL 4 1 -1-1-- 2F DAA 4 1 +-P+++ 27 DEC (HL) 11 1 -1V+++ 35 DEC (IX+N) 23 3 -1V+++ DD 35 XX DEC (IY+N) 23 3 -1V+++ FD 35 XX DEC A 4 1 -1V+++ 3D DEC B 4 1 -1V+++ 05 DEC BC 6 1 ------ 0B DEC C 4 1 -1V+++ 0D DEC D 4 1 -1V+++ 15 DEC DE 6 1 ------ 1B DEC E 4 1 -1V+++ 1D DEC H 4 1 -1V+++ 25 DEC HL 6 1 ------ 2B DEC IX 10 2 ------ DD 2B DEC IY 10 2 ------ FD 2B DEC L 4 2 -1V+++ 2D DEC SP 6 1 ------ 3B DI 4 1 ------ F3 DJNZ $N+2 13/8 2 ------ 10 XX EI 4 1 ------ FB EX (SP),HL 19 1 ------ E3 EX (SP),IX 23 2 ------ DD E3 EX (SP),IY 23 2 ------ FD E3 EX AF,AF' 4 1 ------ 08 EX DE,HL 4 1 ------ EB EXX 4 1 ------ D9 HALT 4+ 1 ------ 76 IM 0 8 2 ------ ED 46 IM 1 8 2 ------ ED 56 IM 2 8 2 ------ ED 5E IN A,(C) 12 2 -0P+++ ED 78 IN A,(N) 11 2 ------ DB XX IN B,(C) 12 2 -0P+++ ED 40 IN C,(C) 12 2 -0P+++ ED 48 IN D,(C) 12 2 -0P+++ ED 50 IN E,(C) 12 2 -0P+++ ED 58 IN H,(C) 12 2 -0P+++ ED 60 IN L,(C) 12 2 -0P+++ ED 68 IN (C) 12 2 -0P+++ ED 70 INC (HL) 11 1 - V + 34 INC (IX+N) 23 3 - V + DD 34 XX INC (IY+N) 23 3 - V + FD 34 XX INC A 4 1 -0V+++ 3C INC B 4 1 -0V+++ 04 INC BC 6 1 ------ 03 INC C 4 1 -0V+++ 0C INC D 4 1 -0V+++ 14 INC DE 6 1 ------ 13 INC E 4 1 -0V+++ 1C INC H 4 1 -0V+++ 24 INC HL 6 1 ------ 23 INC HX 2 -0V+++ DD 24 INC HY 2 -0V+++ FD 24 INC IX 10 2 ------ DD 23 INC IY 10 2 ------ FD 23 INC L 4 1 -0V+++ 2C INC LX 2 -0V+++ DD 2C INC LY 2 -0V+++ FD 2C INC SP 6 1 ------ 33 IND 16 2 -1 + ED AA INDR 21/16 2 -1 1 ED BA INI 16 2 -1 + ED A2 INIR 21/16 2 -1 1 ED B2 JP $NN 10 3 ------ C3 XX XX JP (HL) 4 1 ------ E9 JP (IX) 8 2 ------ DD E9 JP (IY) 8 2 ------ FD E9 JP C,$NN 10 3 ------ DA XX XX JP M,$NN 10 3 ------ FA XX XX JP NC,$NN 10 3 ------ D2 XX XX JP NZ,$NN 10 3 ------ C2 XX XX JP P,$NN 10 3 ------ F2 XX XX JP PE,$NN 10 3 ------ EA XX XX JP PO,$NN 10 3 ------ E2 XX XX JP Z,$NN 10 3 ------ CA XX XX JR $N+2 12 2 ------ 18 XX JR C,$N+2 12/7 2 ------ 38 XX JR NC,$N+2 12/7 2 ------ 30 XX JR NZ,$N+2 12/7 2 ------ 20 XX JR Z,$N+2 12/7 2 ------ 28 XX LD (BC),A 7 1 ------ 02 LD (DE),A 7 1 ------ 12 LD (HL),r 7 1 ------ 7r LD (HL),N 10 2 ------ 36 XX LD (IX+N),r 19 3 ------ DD 7r XX LD (IX+N),N 19 4 ------ DD 36 XX XX LD (IY+N),r 19 3 ------ FD 7r XX LD (IY+N),N 19 4 ------ FD 36 XX XX LD (NN),A 13 3 ------ 32 XX XX LD (NN),BC 20 4 ------ ED 43 XX XX LD (NN),DE 20 4 ------ ED 53 XX XX LD (NN),HL 16 3 ------ 22 XX XX LD (NN),IX 20 4 ------ DD 22 XX XX LD (NN),IY 20 4 ------ FD 22 XX XX LD (NN),SP 20 4 ------ ED 73 XX XX LD A,(BC) 7 1 ------ 0A LD A,(DE) 7 1 ------ 1A LD A,(HL) 7 1 ------ 7E LD A,(IX+N) 19 3 ------ DD 7E XX LD A,(IY+N) 19 3 ------ FD 7E XX LD A,(NN) 13 3 ------ 3A XX XX LD A,r 4 1 ------ 78+r LD A,HX 2 ------ DD 7C LD A,HY 2 ------ FD 7C LD A,LX 2 ------ DD 7D LD A,LY 2 ------ FD 7D LD A,I 9 2 -0+0++ ED 57 LD A,N 7 2 ------ 3E XX LD A,R 9 2 -0+0++ ED 5F LD B,(HL) 7 1 ------ 46 LD B,(IX+N) 19 3 ------ DD 46 XX LD B,(IY+N) 19 3 ------ FD 46 XX LD B,HX 2 ------ DD 44 LD B,HY 2 ------ FD 44 LD B,LX 2 ------ DD 45 LD B,LY 2 ------ FD 45 LD B,r 4 1 ------ 4r LD B,N 7 2 ------ 06 XX LD BC,(NN) 20 4 ------ ED 4B XX XX LD BC,NN 10 3 ------ 01 XX XX LD C,(HL) 7 1 ------ 4E LD C,(IX+N) 19 3 ------ DD 4E XX LD C,(IY+N) 19 3 ------ FD 4E XX LD C,HX 2 ------ DD 4C LD C,HY 2 ------ FD 4C LD C,LX 2 ------ DD 4D LD C,LY 2 ------ FD 4D LD C,r 4 1 ------ 48+r LD C,N 7 2 ------ 0E XX LD D,(HL) 7 1 ------ 56 LD D,(IX+N) 19 3 ------ DD 56 XX LD D,(IY+N) 19 3 ------ FD 56 XX LD D,HX 2 ------ DD 54 LD D,HY 2 ------ FD 54 LD D,LX 2 ------ DD 55 LD D,LY 2 ------ FD 55 LD D,r 4 1 ------ 5r LD D,N 7 2 ------ 16 XX LD DE,(NN) 20 4 ------ ED 5B XX XX LD DE,NN 10 3 ------ 11 XX XX LD E,(HL) 7 1 ------ 5E LD E,(IX+N) 19 3 ------ DD 5E XX LD E,(IY+N) 19 3 ------ FD 5E XX LD E,HX 2 ------ DD 5C LD E,HY 2 ------ FD 5C LD E,LX 2 ------ DD 5D LD E,LY 2 ------ FD 5D LD E,r 4 1 ------ 58+r LD E,N 7 2 ------ 1E XX LD H,(HL) 7 1 ------ 66 LD H,(IX+N) 19 3 ------ DD 66 XX LD H,(IY+N) 19 3 ------ FD 66 XX LD H,r 4 1 ------ 6r LD H,N 7 2 ------ 26 XX LD HL,(NN) 20 3 ------ 2A XX XX LD HL,NN 10 3 ------ 21 XX XX LD HX,r* 2 ------ DD 6r* LD HX,N 3 ------ DD 26 XX LD HY,r* 2 ------ FD 6r* LD HY,N 3 ------ FD 26 XX LD I,A 9 2 ------ ED 47 LD IX,(NN) 20 4 ------ DD 2A XX XX LD IX,NN 14 4 ------ DD 21 XX XX LD IY,(NN) 20 4 ------ FD 2A XX XX LD IY,NN 14 4 ------ FD 21 XX XX LD L,(HL) 7 1 ------ 6E LD L,(IX+N) 19 3 ------ DD 6E XX LD L,(IY+N) 19 3 ------ FD 6E XX LD L,r 4 1 ------ 68+r LD L,N 7 2 ------ 2E XX LD LX,r* 2 ------ DD 68+r* LD LX,N 3 ------ FD 2E XX LD LY,r* 2 ------ DD 68+r* LD LY,N 3 ------ FD 2E XX LD R,A 9 2 ------ ED 4F LD SP,(NN) 20 4 ------ ED 7B XX XX LD SP,HL 6 1 ------ F9 LD SP,IX 10 2 ------ DD F9 LD SP,IY 10 2 ------ FD F9 LD SP,NN 10 3 ------ 31 XX XX LDD 16 2 -0+0-- ED A8 LDDR 21/16 2 -000-- ED B8 LDI 16 2 -0+0-- ED A0 LDIR 21/16 2 -000-- ED B0 NEG 8 2 +1V+++ ED 44 NOP 4 1 ------ 00 OR (HL) 7 1 00P0++ B6 OR (IX+N) 19 3 00P0++ DD B6 XX OR (IY+N) 19 3 00P0++ FD B6 XX OR r 4 1 00P0++ Br OR HX 2 00P0++ DD B4 OR HY 2 00P0++ FD B4 OR LX 2 00P0++ DD B5 OR LY 2 00P0++ FD B5 OR N 7 2 00P0++ F6 XX OTDR 21/16 2 -1 1 ED BB OTIR 21/16 2 -1 1 ED B3 OUT (C),A 12 2 ------ ED 79 OUT (C),B 12 2 ------ ED 41 OUT (C),C 12 2 ------ ED 49 OUT (C),D 12 2 ------ ED 51 OUT (C),E 12 2 ------ ED 59 OUT (C),H 12 2 ------ ED 61 OUT (C),L 12 2 ------ ED 69 OUT (C),0 12 2 ------ ED 71 OUT (N),A 11 2 ------ D3 XX OUTD 16 2 -1 + ED AB OUTI 16 2 -1 + ED A3 POP AF 10 1 ------ F1 POP BC 10 1 ------ C1 POP DE 10 1 ------ D1 POP HL 10 1 ------ E1 POP IX 14 2 ------ DD E1 POP IY 14 2 ------ FD E1 PUSH AF 11 1 ------ F5 PUSH BC 11 1 ------ C5 PUSH DE 11 1 ------ D5 PUSH HL 11 1 ------ E5 PUSH IX 15 2 ------ DD E5 PUSH IY 15 2 ------ FD E5 RES b,(HL) 15 2 ------ CB 86+8*b RES b,(IX+N) 23 4 ------ DD CB XX 86+8*b RES b,(IY+N) 23 4 ------ FD CB XX 86+8*b RES b,r 8 2 ------ CB 8r+8*b RET 10 1 ------ C9 RET C 11/5 1 ------ D8 RET M 11/5 1 ------ F8 RET NC 11/5 1 ------ D0 RET NZ 11/5 1 ------ C0 RET P 11/5 1 ------ F0 RET PE 11/5 1 ------ E8 RET PO 11/5 1 ------ E0 RET Z 11/5 1 ------ C8 RETI 14 2 ------ ED 4D RETN 14 2 ------ ED 45 RL (HL) 15 2 +0P0++ CB 16 RL r 8 2 +0P0++ CB 1r RL (IX+N) 23 4 +0P0++ DD CB XX 16 RL (IY+N) 23 4 +0P0++ FD CB XX 16 RLA 4 1 +0-0-- 17 RLC (HL) 15 2 +0P0++ CB 06 RLC (IX+N) 23 4 +0P0++ DD CB XX 06 RLC (IY+N) 23 4 +0P0++ FD CB XX 06 RLC r 8 2 +0P0++ CB 0r RLCA 4 1 +0-0-- 07 RLD 18 2 -0P0++ ED 6F RR (HL) 15 2 +0P0++ CB 1E RR r 8 2 +0P0++ CB 18+r RR (IX+N) 23 4 +0P0++ DD CB XX 1E RR (IY+N) 23 4 +0P0++ FD CB XX 1E RRA 4 1 +0-0-- 1F RRC (HL) 15 2 +0P0++ CB 0E RRC (IX+N) 23 4 +0P0++ DD CB XX 0E RRC (IY+N) 23 4 +0P0++ FD CB XX 0E RRC r 8 2 +0P0++ CB 08+r RRCA 4 1 +0-0-- 0F RRD 18 2 -0P0++ ED 67 RST 0 11 1 ------ C7 RST 8H 11 1 ------ CF RST 10H 11 1 ------ D7 RST 18H 11 1 ------ DF RST 20H 11 1 ------ E7 RST 28H 11 1 ------ EF RST 30H 11 1 ------ F7 RST 38H 11 1 ------ FF SBC A,(HL) 7 1 +1V+++ 9E SBC A,(IX+N) 19 3 +1V+++ DD 9E XX SBC A,(IY+N) 19 3 +1V+++ FD 9E XX SBC A,r 4 1 +1V+++ 98+r SBC HX 2 +1V+++ DD 9C SBC HY 2 +1V+++ FD 9C SBC LX 2 +1V+++ DD 9D SBC LY 2 +1V+++ FD 9D SBC A,N 7 2 +1V+++ DE XX SBC HL,BC 15 2 +1V ++ ED 42 SBC HL,DE 15 2 +1V ++ ED 52 SBC HL,HL 15 2 +1V ++ ED 62 SBC HL,SP 15 2 +1V ++ ED 72 SCF 4 1 10-0-- 37 SET b,(HL) 15 2 ------ CB C6+8*b SET b,(IX+N) 23 4 ------ DD CB XX C6+8*b SET b,(IY+N) 23 4 ------ FD CB XX C6+8*b SET b,r 8 2 ------ CB Cr+8*b SLA (HL) 15 2 +0P0++ CB 26 SLA (IX+N) 23 4 +0P0++ DD CB XX 26 SLA (IY+N) 23 4 +0P0++ FD CB XX 26 SLA r 8 2 +0P0++ CB 2r SLL (HL) 15 2 +0P0++ CB 36 SLL (IX+N) 23 4 +0P0++ DD CB XX 36 SLL (IY+N) 23 4 +0P0++ FD CB XX 36 SLL r 8 2 +0P0++ CB 3r SRA (HL) 15 2 +0P0++ CB 2E SRA (IX+N) 23 4 +0P0++ DD CB XX 2E SRA (IY+N) 23 4 +0P0++ FD CB XX 2E SRA r 8 2 +0P0++ CB 28+r SRL (HL) 15 2 +0P0++ CB 3E SRL (IX+N) 23 4 +0P0++ DD CB XX 3E SRL (IY+N) 23 4 +0P0++ FD CB XX 3E SRL r 8 2 +0P0++ CB 38+r SUB (HL) 7 1 ++V+++ 96 SUB (IX+N) 19 3 ++V+++ DD 96 XX SUB (IY+N) 19 3 ++V+++ FD 96 XX SUB r 4 1 ++V+++ 9r SUB HX 2 ++V+++ DD 94 SUB HY 2 ++V+++ FD 94 SUB LX 2 ++V+++ DD 95 SUB LY 2 ++V+++ FD 95 SUB N 7 2 ++V+++ D6 XX XOR (HL) 7 1 00P0++ AE XOR (IX+N) 19 3 00P0++ DD AE XX XOR (IY+N) 19 3 00P0++ FD AE XX XOR r 4 1 00P0++ A8+r XOR HX 2 00P0++ DD AC XOR HY 2 00P0++ FD AC XOR LX 2 00P0++ DD AD XOR LY 2 00P0++ FD AD XOR N 7 2 00P0++ EE XX ========------====-====-======--=======-------- Mnemonic Time Size CNPHZS OP-Code ³³³³³³ Bit 0 CarrY ÄÙ³³³³³ Bit 1 (N) add/subtract ÄÄÙ³³³³ Bit 2 Parity/oVerflow ÄÄÄÙ³³³ Bit 4 Half Carry ÄÄÄÄÙ³³ Bit 6 Zero ÄÄÄÄÄÙ³ Bit 7 Sign ÄÄÄÄÄÄÙ +:Affected -:Unaffected 1:Set 0:Reset r means register (A,B,C,D,E,H,L) (r* register H/L are HX/LX) Add this to last byte of OP-code: r nibble r* nibble A = 7 A = 7 B = 0 B = 0 C = 1 C = 1 D = 2 D = 2 E = 3 E = 3 H = 4 HX = 4 L = 5 LX = 5 ( (HL) = 6 ) b means bit (can be 0-7 - well duh) Increase the last byte of OP-code with 8*b If there is two numbers given at Clock then the highest is when the jump is taken Unsupported instructions: (use op.codes) SLL = shift left logical, bit 0 is set LX/HX/LY/HY = low-/high-order 8 bits of IX/IY OUT (C),0 IN (C) By SHIAR (shiar@mailroom.com) used data from: * z80time.txt by Oscar Lindberg * z80iss.txt by Jonathan Bowen z80opcod.txt by Herbert Oppmann z80instr.txt by Unknown