Multigame Needs mcr2 Video Board 8k X 32 bits per game (256 kbits) CPU Board 48k X 8 bits per game (384 kbits, probably will round to 512 kbits) CPU Board (Background Roms) 8k X 16 bits per game (128 kbits) Sound Board 16k X 8 bits per game (128 kbits) For 8 games possible minimum devices needed are: Video Board : 4 64k X 8 bit devices (512kbit devices, 32pin) CPU Board : 1 512k X 8 bit device (4Mbit device, 32pin) FG Roms : 2 64k X 8 bit devices (512kbit devices, 32pin) Sound Board : 1 128k X 8 bits device (1Mbit device, 32pin) For 16 games possible minimum devices needed are: Video Board : 4 128k X 8 bit devices (1Mbit devices, 32pin) CPU Board : 2 512k X 8 bit device (4Mbit devices, 32pin) FG Roms : 2 128k X 8 bit devices (1Mbit devices, 32pin) Sound Board : 1 256k X 8 bits device (2Mbit device, 32pin) Game Order: 0 - Tron 1 - Two Tigers Yoke 2 - Satans Hollow 3 - Wacko 4 - Domino Man 5 - Kozmik Krooz'r **note must ground J4:13 to get game to boot (rotate spaceship fix) 6 - Two Tigers Spinner 7 - Empty CMOS RAM Replacement As with the williams multigame, I am using a simtek NVRAM chip which has extra space to hold each games settings and scores. A socket adapter will replace the existing ram chip. The 16c88 is perfect with enough room for 16 games. Rom Signals Location Foreground Roms (Video Board) Address ROMAD0- ROMAD12 (Vid Board, 28pin Socket A1) Data RD0 - RD31 (Vid Board, 28pin Socket A1, B1, D1, E1) Output Enable GND (Always Output) Chip Select GND (Always Enabled) Game Select Bus Bits A13-A15 Background Roms Address PA0 - PA12 (CPU Board, 28pin Socket G3) Data 2 X (D0 - D7) to Specific Logic (CPU Board, 28pin Socket G3 & G4) Output Enable GND (Always Output) Chip Select GND (Always Enabled) Game Select Bus Bits A13-A15 Program ROM Address BuA0 - BuA12 (CPU Board, 28pin Socket D2) Additonal Address Bits Needed BuA13 - BuA15 (CPU Board, 28pin E6 Solder) Data BuD0 - BuD7 (CPU Board, 28pin Socket D2) Output Enable Sel0=Low - Sel5=Low (Any) Chip Select Sel0=Low - Sel5=Low (Any) (CPU Board, E6 Solder) Game Select Bus Bits A16-A18 Sound Rom Address BSA0,BSA1,BA2 - BA11 (Sound Board, 24pin Socket A7) Additonal Address Bits Needed BA12 - BA13 (Sound Board B12, Solder) Data BSD0 - BSD7 (Sound Board, 24pin Socket A7) Output Enable None On Device TT Board is misjumpered with A11 going to VPP Pin 18. Odd. I can use this signal!! I need it since A11 is tainted by CS on individual chips For multirom I will use: Rom0=Low - Rom3=Low (Any) Chip Select Rom0=Low - Rom3=Low (Any) (Sound Board B12, Solder) Game Select Bus Bits A14-A16 approx 10 wires require soldering, all others are jumping into sockets. 1 7408 quad 2-input AND should handle chip select for the sound rom and 1 7411 triple 3-input AND should handle chip select for the program rom If I scan the necessary inputs for all games, I need an 8 X 9 input matrix. There are too many output pins that need to be driven for the uC to handle, so one input micro and one output micro will be used They will communicate with a (up to) 5 MHz SPI serial bus (I may slow this for stability). The micro of choice is the pic16f877. PIC 1 Functionality * Designate active game with Game Select Bus (3 pins for bus) * Handle game switching and boardset reset (1 more Pin for reset) * Read input from various input devices using scanned matrix. (8 + 9 pins) * Translate inputs to correct input pin on SSIO board * Send Data to be latched to PIC 2 via SPI bus (3 pins for serial bus) ? Remember last game played (easy to do, do I want it?) and boot to it on powerup PIC 2 Functionality * Wait for commands to arrive on SPI bus * Update Output pins as commanded * 30 Output pins may be utilized ROM Pinouts __ __ __ __ A7| U |+5V A7| U |+5V A6| |A8 A6| |A8 A5| |A9 A5| |A9 A4| |A11 A4| |+5V A3| 2 |!CS A3| 2 |!CS A2| 7 |A10 A2| 5 |A10 A1| 3 |!CE A1| 3 |A11 A0| 2 |D7 A0| 2 |D7 D0| |D6 D0| |D6 D1| |D5 D1| |D5 D2| |D4 D2| |D4 GND|_____|D3 GND|_____|D3 +--------------+ VPP |1 +--+ 28| VCC A12 |2 27| /PGM A7 |3 26| A6 |4 25| A8 A5 |5 24| A9 A4 |6 23| A11 A3 |7 2764 22| /OE A2 |8 21| A10 A1 |9 20| /CE A0 |10 19| D7 D0 |11 18| D6 D1 |12 17| D5 D2 |13 16| D4 GND |14 15| D3 +--------------+ +--------------+ A7 |1 +--+ 24| VCC A6 |2 23| A8 A5 |3 22| A9 A4 |4 21| /WR A3 |5 20| /RD A2 |6 19| A10 A1 |7 B2 18| /CS A0 |8 CMOS 17| D7 D0 |9 RAM 16| D6 D1 |10 15| D5 D2 |11 14| D4 GND |12 13| D3 +--------------+