williams    Well, I ve been fixing some Robotrons for Dave, and some of them 
really have me stumped.  This has lead me to pouring over the schematics time 
and time again, and guess what?  Some of it actually sunk in.  So my intent here 
is to talk alittle about the various sections of the schematics and what certain 
chips do.  With luck this may help others to narrow down problems. 
        A quick note...I have used Sean Riddles page extensivley for my 
multigame, as he talks alot about S/W and addressing, but specifically on a 
slant towards his well done multigame.  I wish to talk here more about what the 
different chips do, to help others in problem solving. 
Copywrite:  At this point, I offer this text in its entirety, to all who may 
make use of it.  Please quote the author if it is reproduced. 
Disclamer:  These are my Ramblings.  If you use the information ,I take no 
responsibilty in it accuracy, and will not be held resposible for any damage 
caused by its use!  If you find an error (and I'm sure there are some) tell me! 
Section 1 - Memory Errors 
    Got a 1-3-1 error?  For Gods sake don't start throwing out chips (mail them 
to me ;-) ).  When the ram is checked via self test, the first chip done is 3-1. 
 If this chip is reported bad, it is almos always a power related problem.  
Chckt the voltages right on the pins of the RAM. 
    1 - -5 v 
    8 - +12 v 
    9 - +5 v 
    16 - Ground 
    If there is a missing voltage, shut her down.  Leaving the power on too long 
with a missing -5 can damage these pesky RAM chips.  Check the supply, moreover, 
check the connector to the main board and the solder job on the underside of the 
board.  The joints have a habit of cracking. 
    To move on, the self test does 3-1, 3-2, ...3-8, 1-1, 1-2, ...1-8, 2-1, 2-2, 
...2-8.  So if a memory location fails, swap the suspect chip to any location 
already tested.  If the problem moves with the chip, replace it.  If it stayes 
in that location, you may have a bigger problem.  I cannot suggest exactly what 
to look for, but read on to the point where I talk about memory access. 
Section 2 - Memory Addressing... 
    There are two potential users of memory on the system.  The CPU and the 
Video Output.  The btw correlates to having 2 video decoder ROMS.  Lets talk 
first about the CPU. 
    If the CPU wants to get at the RAM , it uses A8 to A15 and A0 to A7.  The 
higher bits are first put through the video decoder ROM at 3G to produce a 
column address select byte (CAS) and the lower bits are used as row address 
select bits (RAS).  Actually since the RAM only needs 7 lines, A0 is used at the 
bit 7 (MA6) of the CAS, and only D0 - D5 are used for CAS out of the decoder 
ROM. 
    The 74153's are toggled to select one of 4 output scenarios.  CPU address 
lines RAS and CAS, or video address lines to the CAS and RAS.  Now these address 
lines are presneted to every ram chip, and every ram chip then outputs its data 
on to its own little bus.  If the CPU wants the data, it will enable the 
74LS374's corresponding to the bank it wants and the data is then put onto the 
main data bus.  Alternatively, the CPU can select the write enable lines (so can 
the blitter chips) to put data from the main data bus into the RAM chips for a 
particular bank.  As you may or may not be able to see thare are many possible 
points of failure in this loop.  History has shown that the '374's will fail 
from time to time causing the CPU to report bad memory chips. 
    The video output is a bit different however...There are 4 binary counters 
constanly couting up, then getting reset.  The output of this count drive, among 
other things, address lines gor the memory (RAS) and the decoder at 3C (CAS).  
When the '153's are passing this data through, the memory output goes down to 8 
74166's.  One bank of 4 is for normal mode, the other is for cocktail flip 
screen mode.  These chips are clocked at 6 MHZ and simply shift the data out in 
4 bit blocks to the 74LS257 (which appears to only select which bank of 4 166's 
to select from for flip screen).  This data is then fed to the 74LS257 at 2C.  
2C is the chip responsible for feeding the 7489's either address lines od the 
RAM data.   The 7489's are the colour look up RAMS, which take the 4 bit info 
from the '257 and produces 8 bits of colour (two banks 7489's) and that 8 bits 
of colour ar buffered to the transistors which control the intensity of the  RGB 
output.  Alternativly, the 2C chip can send address data to the 7489, in 
conjuction with the CPU setting up the data to write to the RAM.  In this manner 
the CPU can dynamically alter the colour pallet, choosing from 256 colours to 
get a max of 16 colours out on the screen at a time. 
Section 3 Sync... 
  
    It is well documented that the Williams games have pin 7 ov the video output 
as Composite Sync (positive).  Too bad williams did not document this.  Another 
documented fact (Joust to Jamma) is that in order to produce a negative comp 
sync, you simply (?) add an inverter to this.  I think I have found an easier 
way. 
    On the schematics, there is a zero ohm resistor called W1 on the input to 
the 4 XOR gates ar 4A.  This is incorrect.  W1 is actually a jumper off of 6A.  
The incorrect W1 is actually a trace on the board under resistor R34.  This 
trace, when intact has the function of making R34 useless.  It has one end on 
ground (via the trace) and the other tied at 5 volts.  The trace then holds the 
second input to 3 of the four XOR gates low, and by definition, the XOR gates 
are reduced to a buffer.  These gates are Comp sync, H Sync and V Sync.  If we 
now cut the trace, R34 is now a pull up resistor , making the second input to 
the 3 XOR gates high, and again, by definition makes the XOR gates into NOT 
gates.  Voila - negative Comp sync.  Works Great.