Subject: PHOENIX reeng.
Date: 26 May 1996 23:46:41 GMT
Newsgroups: rec.games.video.arcade.collecting

Hello Folks,

I recently took a closer look at the PHOENIX schematics for repair purposes
and wrote down the results. The circuitry look simple enough for being
emulated without much trouble.
Maybe someone likes to put in some time ?

Btw., how about creating an schematics/reengineering archive on wiretap for
future arcade simulations (i.e. making scans of YOUR schematics) ?? 

Regards,

	Ralph

reply-to: [email-masked] (Ralph Kimmlingen)

			---------------------------------
			  -----------------------------
			     ------------------------
			  ---------> PHOENIX <---------
			     -----------------------
			  -----------------------------
			---------------------------------
		
		 	   --------------------------
			        -----------------
			          Reengineering 
		            	  Project  '96
			        -----------------
			   --------------------------

			    ----------------------
				 ------------
				   Hardware
				 ------------
			    ----------------------
			
Components
----------

- 8085 CPU @5.5 Mhz
- 8x2kB ROM
- Two plane display (CHARSET-A, CHARSET-B)
  CHAR-A: 2x2kB ROM, 4x0.5kB RAM
  CHAR-B: 2x2kB ROM, 4x0.5kB RAM
- 2x3 bit color DAC
- 8 bit vertical scroll register
- MN6221AA 2voice melody module

please note: as Phoenix uses a 90 degree rotated picture tube, all 
             references to 'horizontal' positions actually mean VERTICAL
	     ELECTRON BEAM positions.

Functionality
-------------
The picture consists of two independent planes, where each pixel is represented
by two bits. As the lower plane is used for scrolling (CHAR-A, starfield),
the first row is always invisible (scroll-buffer).
All sprites and text are displayed in the upper plane (except for eagles).

_____26x8 pixel___________
|xxxxxxxxxxxxxxxxxxxxxxxx| <-- first row (score count etc.)
|			 |
|			 |
|    /+\		 |
.			 .
:			 : <32x8 lines>
			
|     |			 |
|			 |
|     |	 		 |
|     			 |
|_____^__________________|

The graphic data for each plane is drawn from a 8x8 charset and an attached
video ram of 2x1024 bytes. Only 26*32 bytes are actually used, representing
a screen size of 26*32 characters. 
Each video ram consists of two banks, which allows for double buffering (see
video control register).
Vertical scrolling is controlled by a 8 bit value, which determines the 
first line to be drawn by the video logic. Example:

scrollreg= 9 --> video logic starts reading video ram at byte 32 and
		 charset-rom at the second byte.
		 After finishing row 26, row 0 is drawn (->wraparound).

Colors
------
Two 8-to-3 lookup-tables (PAL's) are responsible for color output. These PAL's 
allow for a palette of 6 bit (64 colors) :

7 bit value -->  Lookup-Table1  --> 3x1bit (RGB) --> DAC ] video out
7 bit value -->  Lookup-Table2  --> 3x1bit (RGB) --> DAC ] (RGB)

							RED	BLUE 	GREEN
							2bit	2bit	2bit	

The 8 bit value for lookup tables is composed of the following signals:

Bit	from
---------------
0	 ]
1	 ] bit 5-7 of video ram value (divides 256 chars in 8 color sections)
2	 ] 
3	] 2 bit pixelcolor
4	] (either from CHAR-A or CHAR-B, depends on Bit5)
5	0= CHAR-A, 1= CHAR-B 
6	palette flag (see video control reg.)
7	always 0

Memory Map
----------

0000-3fff	16kB ROM (code + tables)

4000-43ff	RAM A (1kB)
		lower 32x26 bytes used for video ram (CHAR-A),
		remaining 192 bytes for variables		

4800-4bff	RAM B (1kB)
		lower 32x26 bytes used for video ram (CHAR-B),
		remaining 192 bytes for variables		

5000		2 bit video control register (write only)
		Bit	Used for
		---------------
		0	switching between VIDEO RAM banks (double buffering)
			 0: r/w access to 4000-43ff or 4800-4bff
			    is directed to bank0
			 1: r/w access to 4000-43ff or 4800-4bff
			    is directed to bank1
   		1	color palette swap (blue/red eagles etc.)
			this bit represents A6 of color PAL chip
		2-7	not used
5000-53ff	video control (mirrored)

5800		8 bit vertical scroll register (CHARSET-B)
		this value determines the first of 32x8 vertical pixels
		to be shown (wraparound fashion)
5800-5bff	scroll register (mirrored)

6000		sound control A
		Bit	Used for
		---------------
		0	]
		1	] frequency voice1
		2	] 
		3	]
		4	 ] volume voice1 (probably)
		5	 ] 
		6	] melody module command:
		7	] { <silence>, <for luise>, <???>, <alarm beep> }
6000-63ff	sound control A (mirrored)

6800		sound control B
		Bit	Used for
		---------------
		0	]
		1	] frequency voice2
		2	] 
		3	]
		4	 ] volume voice2 (probably)
		5	 ] 
		6	] noise channel (probably volume 0-3)
		7	]
6800-6bff	sound control B (mirrored)

7000		8 bit game control (read only)
		Bit	Used for
		---------------
		0	coin
		1	start1
		2	start2
		3	-
		4	fire
		5	right
		6	left
		7	barrier
7000-73ff	game control (mirrored)

7800		8 bit dip-switch (read only)
		Bit	Used for
		---------------
		0	dip-settings
		1	dip-settings
		2	dip-settings
		3	dip-settings
		4	dip-settings
		5	dip-settings
		6	dip-settings
		7	for video ciruits : flip picture vertical
			when read by CPU:
			 ->horizontal sync: this signal is logical HIGH
				         during video output of row 0*8-25*8,
				         otherwise LOW.
7801-7bff	dip-switch (mirrored)