Source: Mapping the Atari, by Ian Chadwick
D200 (W): AUDF1 D201 (W): AUDC1 D202 (W): AUDF2 D203 (W): AUDC2 D204 (W): AUDF3 D205 (W): AUDC3 D206 (W): AUDF4 D207 (W): AUDC4 D208 (W): AUDCTL D209 (W): STIMER D20A (W): SKREST D20B (W): POTGO D20C: (unused) D20D (W): SEROUT D20E (W): IRQEN D20F (W): SKCTL D200-D207 (R): POT1-POT7 D208 (R): ALLPOT D209 (R): KBCODE D20A (R): RANDOM D20D (R): SERIN D20E (R): IRQST D20F (R): SKSTAT
Audio channel 1 period multiplier. (The mnemonic AUDio Frequency 1 is a misnomer, although easier to understand.) This register + 1 defines the number of pulses from the Pokey clock that will be counted before toggling the output of this channel from low to high or from high to low. In other words, this number (+1) multiplied by the period of the Pokey clock in use gives half the period of the output waveform.
For example, to determine the period multiplier for an A note (440 Hz by definition) using an input clock of 64KHz, the formula is:
63920 / 440 / 2 - 1 = 145.3 / 2 - 1 = 72.64 - 1 = 71.64
which means the closest we can get is 72 (actually 437.8 Hz).
Same as AUDF1. (Needs more research): It is also used with AUDF3 to store the SIO baud rate.
Same as AUDF1. (Needs more research): It is also used with AUDF2 and AUDF4 to store the SIO baud rate.
Same as AUDF1. (Needs more research): It is also used with AUDF3 to store the SIO baud rate.
| Distortion | Volume Only | Volume Level |
Distortion: The output waveform is masked by Pokey's polynomial (random) counters such that a low to high transition is only made if the polynomial output bit is 1. A high to low transition is always made. The counters used to mask the output are selected with the distortion bits as follows:
0: 5-bit and 17-bit counters
1: 5-bit counter
2: 5-bit and 4-bit
counters
3: 5-bit counter
4: 17-bit counter
5: none (pure
tone)
6: 4-bit counter
7: none (pure tone)
Volume Only: If this bit is set, the AUDFn register and distortion bits are ignored. Instead, the output for this channel is kept at a flat level specified by the volume register.
| 9-bit Poly | 1.79MHz Ch.1 | 1.79MHz Ch.3 | Join 1-2 | Join 3-4 | High-pass 1-3 | High-pass 2-4 | 15KHz Clock |
9-bit Poly: If set, only 9 bits in the 17-bit polynomial counter are used, resulting in a shorter period of repetition.
1.79MHz Ch.1: If set, channel 1 will be clocked by 1.790 MHz instead of the main clock. Also, the period counter is offset from the actual period by 4 instead of 1 (or 7 if using 16-bit counters).
1.79MHz Ch.3: If set, channel 3 will be clocked by 1.790 MHz instead of the main clock. Also, the period counter is offset from the actual period by 4 instead of 1 (or 7 if using 16-bit counters).
Join 1-2: If set, channels 1 and 2 will be joined into a single 16-bit period multiplier, with channel 1 as the low byte and channel 2 as the high byte. This allows a much greater frequency range, and when used in conjunction with the 1.79MHz clock, give you more precision in output frequencies. For example, the A note can be defined as:
1789772.5 / 440 / 2 - 7 = 4067.7 / 2 - 7 = 2033.8 - 7 = 2026.8
So if we set it to 2027, the actual frequency will be 439.96, which is almost perfect!
Join 3-4: If set, channels 3 and 4 will be joined into a single 16-bit period multiplier, with channel 3 as the low byte and channel 4 as the high byte. This allows a much greater frequency range.
High-pass 1-3: (Needs more research): If set, the channel 1 will only play if its period is less than that of channel 3.
High-pass 2-4: (Needs more research): If set, the channel 2 will only play if its period is less than that of channel 4.
15KHz Clock: If set, the main audio clock will be 15.700 KHz. If clear, the main audio clock will be 63.920 KHz.
Writing any non-zero value to this register will reset all the audio clock counters to the values in AUDFn.
Writing to this register will reset SKSTAT bits 5-7.
Writing to this register will reset the POTn registers to 0, discharge the capacitors and start to rescan the potentiometers.
Data written here is placed in a serial shift register to be transmitted via the SIO port.
| BREAK Pressed | Key Pressed | Serial Input Ready | Serial Output Data Needed | Serial Output Done | Timer 4 | Timer 2 | Timer 1 |
Interrupt enable bits. If a bit is 1, the corresponding interrupt type is enabled.
| Force Break | Serial Port Mode Control | Two-tone Mode | Fast POT Scan | Keyboard Scan | Keyboard Debounce |
Force Break: If set, the serial output line will be held at zero.
Serial Port Mode Control: Set the serial clock lines as follows:
(Needs more research)
Two-tone Mode: If set, serial output is transmitted as a two-tone signal, used for writing data to a cassette. If clear, data is transmitted as logic true/false.
Fast POT Scan: If set, the POT scan completes in two scan lines, but is not very accurate. If clear, the POT scan completes in 228 scan lines.
Keyboard Scan: Enables keyboard scanning.
Keyboard Debounce: Enables keyboard debounce ciruits.
(Needs more research): Potentiometer reading. There are two pots for each game port -- the even numbered pot is the left paddle, and the odd numbered pot is the right paddle. For Atari paddles, the reading varies from 228 at the furthest counterclockwise position to 0 at the furthese clockwise position. These registers are reset to 0 whenever POTGO is written, after which they slowly increase until the resistance level of the potentiometer is reached.
| Pot 7 | Pot 6 | Pot 5 | Pot 4 | Pot 3 | Pot 2 | Pot 1 | Pot 0 |
Pot n: Ready state of the POTn registers. If the bit is 1, the corresponding register's value is valid. If the bit is 0, the register is in the middle of counting.
Holds the keyboard code of the last key kit.
Reads the high order 8 bits of the 17-bit polynomial counter. Since the polynomial counter is updated every clock cycle (1.79MHz), the value of this register can be considered truly random because of the inaccurate timing with which the CPU can read the data.
Data in the serial input shift register can be read here after the full byte is received.
| BREAK Pressed | Key Pressed | Serial Input Ready | Serial Output Data Needed | Serial Output Done | Timer 4 | Timer 2 | Timer 1 |
Interrupt status bits. If a bit is 0, the corresponding interrupt type has occurred.
| Serial Input Frame Error | Serial Input Overrun | Keyboard Overrun | Ignore Shift Register | Shift Key | Key Pressed | Serial Input Busy | unused |
Serial Input Frame Error: There were missing or extra bits in the current serial byte. This bit must be reset by writing to SKREST.
Serial Input Overrun: The data in the shift register was not read from SERIN before the next byte started coming in. This bit must be reset by writing to SKREST.
Keyboard Overrun: The data in the keyboard register was not read from KBCODE before the next key was pressed. This bit must be reset by writing to SKREST.
Ignore Shift Register: If this bit is clear, data can be read directly from the serial input port rather than waiting for it in SERIN.
Shift Key: If this bit is clear, one of the Shift keys is being held down.
Key Pressed: If this bit is clear, one of the normal keys is being held down.
Serial Input Busy: If this bit is clear, the shift register is in the middle of receiving a byte from the serial input.