Subject: TECH: Inside the WPC Switch Matrix
From: Clive Jones <[email-masked]>
Date: Mon, 29 Apr 96 08:04:00 PDT
Newsgroups: rec.games.pinball

Well, were having the hottest days of the year so far in the UK (were I   
am anyway) which has just presented my workshop with a little problem,   
forget Attack from Mars - my workshop has been attacked by wasps!

So I thought,- it's time for another tech ramble, and left my workshop in   
a hurry after leaving the wasps a calling card courtesy of that curry I   
had the night before - if that doesn't kill them I don't know what will!   
(it made *me* feel physically sick!!!).

Anyway, following on from the article on Microprocessors in pinball, I   
was asked if I would produce an article on how a switch matrix works - so   
here it is. Tonights episode - the WMS WPC switch matrix (just for all   
you RGP'ers with modern games).

If your a beginner, and you look at the WPC circuit below, I'm betting   
that your going to be somewhat confused - I know *I was* when I first   
encountered a circuit like this some years ago. The problem with this   
circuit involves actually knowing what goes in inside a ULN-2803 and more   
importantly the LM339 Quad comparator.

To fully understand the circuit we need to describe how a comparator   
works. A comparator has two inputs - inverting (-) and non-inverting (+)   
and of course an output. lets deal with the inputs first.
If the voltage at the *inverting* pin is greater than the voltage at the   
*non-inverting (+)* pin the output of the comparator will go low, this   
way a 'threshold' voltage can be set up on the non-inverting input which   
when excedeed on the inverting input, causes the comparator to change   
state. The output of the LM339 has an *open collector* - this is by far   
the most *important* aspect of this circuit and also applies to the   
ULN-2803 too (for which I didn't have a data sheet handy so I'm guessing   
a bit, but, it shouldn't effect the following circuit description).

Whats an open collector output? - well, the chips output stage has an   
in-built NPN transistor, who's collector is actually connected to the   
output pin of the LM339 (pins 1, 2, 13 and 14 - there are *4* individual   
comparators in a LM339 package) when you connect the output up in a   
circuit, you are actually connecting it to the collector of a transistor!

When the transistor switches on, it will 'sink' to ground the signal   
connected to it - in the WPC switch matrix circuit this will be the 5   
volt strap via the pull-up resistor 'R30', this will cause the previously   
high output (set via R30) to go low. This output is actually also the   
input to our inverter IC at U13 too.

For open collector circuits to operate correctly they *must* have a   
pull-up resistor on the output to give two defined states - high via the   
resistor strap and low when the transistor grounds.

For and 8 x 8 switch matrix there are obvioulsy 8 column stages and 8 row   
stages - notice I haven't used the word 'drivers' - simply because one of   
the best aspects of this circuit involves the fact that it doesn't have   
any! - the matrix is supplied *directly* from the 12 volt line via the   
pull-up resistors R67 and to a lesser degree R52. The TTL IC's used in   
the WPC cannot handle 12 volts directly - they are 5 volt devices, in   
fact, if you shove 12 volts into any 'ls' (low power schottky) device -   
you get a 'supermodel'. - nice legs but no body. By using the 2803 and   
LM339 at 12 volts and the 'ls' devices at 5 volts, we have a   
'level-shifting' interface in action here - 12 volts down to 5 volts for   
our digital logic to safely read.

The switches are arranged a matrix of 8 x 8 with a diode assigned to each   
switch which prevents it influencing another line should it close - this   
is standard matrix stuff and applies to most pinball switches under uP   
control;

+ = intersection

row 0 +--------------+--------------+--------------+---------------->
      |        __    |        __    |        __    |        __
      '--[>|--O  O-. '--[>|--O  O-. '--[>|--O  O-. '--[>|--O  O-.(s5-s8)
               s1  |          s2  |          s3  |          s4  |
                   |              |              |              |
row 1 +----------- |-+----------- |-+----------- |-+----------- |-->
      |        __  | |        __  | |        __  | |        __  |
      '--{>|--O  O-+ '--[>|--O  O-+ '--[>|--O  O-+ '--[>|--O   
 O-+(s13-s16)
               s9  |         s10  |         s11  |         s12  |
                   |              |              |              |
                column0        column1        column2        column4.....

Okay lets explain all this in more detail, forget about the two 470   
picofarad capacitors - there involvement here is purely a decoupling one   
and does not effect the theory of circuit operation. Here comes the   
obligatory ASCII schematic (ASCII does not lend itself well to this kind   
of stuff unfortunately - that's a cop-out excuse for "clive your crap at   
drawing");

*The WPC Switch Matrix Circuit*

(this is a *real* WPC matrix by the way - not an example)

     *COLUMN*
 (typically 8 off)            +12V
 ___                    R67    |
|   |  ULN-2803     .--[ 1K ]--'
|   |     |\        |                /       matrix
|   |9   1| \18     |               /        diode
|U14|-----|  >O-----+------>Jx>----O SW1 O----|<]---->Jx>-.
|   |     | /       |                                     |
|   |     |/ U20    |                                     |
|   |               '---|470|---.                         |
|___|                    pf     |                         |
LS374                          0V                         |
                                                          |
                                                          |
                                                          |
                                                          |
             +5V                                          |
              |                                           |
              +------------------.      *ROW*             |
              |                  | (typically 8 off)      |
      ___     |  R30             |                        |
     |   |    +-[10K]-.          |                +12V    |
     |   |    |       |          |                  |     |
     |   |    |       |     /|10 |           R52    |     |
     |   |    |       |    /-|---'      .---[1K2]---'     |
o/p  |   |11  |       | 13/  |          |                 |
<---O|U13|----+-------+--<   |          |    D1           |
     |   |                \  |11  R51   |  1n4148         |
     |   |          U18    \+|--[1K ]---+---[>|-----------'
     |   |         LM339    \|          |
     |   |         (1/4)                |
     |___|                              |
     LS240                              '---|470|---.
                                             pf     |
                                                    |
                                                   0V

*I should tidy up one point here - there is only ONE 74ls374 octal latch   
and ONE 74ls240 octal inverting driver in the WPC switch matrix, each   
have 8 individual latches/inverters respectively within their chips to   
cope with the 8 columns and 8 rows*

*Full circuit description*

The WPC 6809 uP in conjunction with the WPC ASIC, selects each line to   
*scan* by writing an active bit (high or '1') to the latch at U14   
(74ls374*), which is connected to the ULN-2803 (U20) *open-collector   
inverter* at pin 1 (latches are used so that the uP can check the output   
state at the other end without having to hold the scan line high itself -   
it may go off and perform other duties before returning to examine the   
result the other end?).

[*The 74ls374 is an octal (8 off) 'D' type latch. If the 6809 uP writes   
an active bit to one of the latches, it is passed to the 'Q' output which   
*holds* it high ('latches' it) regardless of whether the 'D' input   
changes state (goes low or tri-state or whatever) providing the clocking   
and hold criteria is met. 'D' type latches such as this are known also as   
'1 bit stores'.]

When the 2803 switches state, it pulls the 12 volt strap via R67 low   
using the internal NPN transistor, thereby depriving that matrix line of   
power. If the matrix switch is open then the comparator side of the   
circuit is uneffected (it's simply not *connected* as the switch is   
*open*), the uP will then check the output of the 74ls240 *inverting*   
octal driver at U13 the other end for a change of state (going from low   
for an open switch to high for a closed switch).

[The output of the comparator is held high via R30 so this immediately   
translates to a low signal being outputted by the 74ls240 under normal   
conditions with the switch *open*.]

<here's the juicy bit>

No then, if the switch is closed and the WPC writes an active bit to the   
latch at U14, the 2803 changes state, pulls the 12 volt strap and the   
matrix line low and *also* pulls the *non-inverting* input of the LM339   
comparator low because it's connected throught the switch, which means   
that the *inverting* input now has a higher voltage (it's connected   
directly to 5 volts), forcing the LM339 output to go low (the internal   
transistor turns on and grounds the 5 volt strap via R30) - this   
translates to the output of U13 going high (it's an inverter remember),   
which the 6809 uP reads as a valid switch closure.

<the juicy bit just ended>

Did you get that?

The scanning method would involve writing an active bit to the first   
column latch at U14 and checking all 8 rows then other end for a change   
of state (from low to high), then advancing to the next column and doing   
the same thing until all 8 columns had been scanned - 8 columns x 8 rows   
= 64 switches.

Note also that the pull up resistors are limiting the amount of current   
into the LM339 output;

5 volts / 10,000 ohms = 500 uA (this current is actually more to do with   
the safe *input* current for the 74ls240).

and the ULN-2803;

12 volts / 1000 ohms = 12mA (which is actually the approx. matrix   
current).

Time for a beer.

Clive
<[email-masked]>

[Not to be sold for profit, circuit copyright WMS, used without their   
permission (hey it's free advertising for WMS right?). I am in no way   
associated with Williams (unfortunately), except for the fact that I own   
a few of their games, but, if they want to send me ton's of pinball   
related mechandise or a few Beta games - you know where I am!]