From: FranklinBowen@hotmail.com (Franklin Bowen) Newsgroups: rec.games.video.arcade.collecting Subject: A little Williams information for everyone Date: 29 Jun 2004 17:35:20 -0700 This stuff is probably a great big for experienced RGVACers but I wrote it up at some point with the intent of creating YAWP (Yet Another Williams Page). The web page does not look like it is happening so I post the information here for the community to do with as it pleases. Enjoy! PS This information could contain errors so use it at your own risk! You have been warned so if your machine blows up because of something in this text, I will not be held responsible. Chip equivalents: ================= 8T97 = 74367 2/4-bit buffers (this chip can also be replaced by a 74365 since both enable pins are driven by the same signal) 9316 = 74161 binary counter Glossary: ========= See http://members.cox.net/seanriddle/glossary.html first. I only have things that Sean did not cover. A15-A0: The 16 address lines. 15 is most significant bit and 0 is least significant bit AVMA: Advanced Valid Memory Address D7-D0: The 8 data lines. 7 is most significant bit and 0 is least significant bit EVIE: ? Address Decoding: ================= The 74154 on the ROM board uses A15-A12 to break down the 64K address space into 16 4K chunks. Dxxx-Fxxx are ROMs only (except for Sinistar which substitutes a SRAM and the circuitry to drive it at Dxxx). 0xxx-8xxx are shared by ROM space and RAM so all writes in that space go to RAM and reads choose between RAM and ROM. The 4K of address space at Cxxx is called the I/O address space. A11-A8 are used by some 74139s to break down the I/O address space into smaller chunks. On the ROM board, if A11 is high and A10 is low, the B side (high numbered pins) of the 74LS139 at 3B (7E on Sinistar) enables the A side (low numbered pins) of the same 74LS139. If A9 & A8 are low (C8xx), the 6821 (PIA) at 1B (8C on Sinistar) is selected (A2 & A3 need to be high too in order for the 6821 to be activated). If A9 is low and A8 is high (C900), the screen control flip-flop at 3A (8F on Sinistar) is selected. If A9 is high and A8 is low (CA00), the special chips at 8A & 9A (1F & 2F on Sinistar) are selected. The I/O signal also goes to the CPU board where it enables some 74LS139s that also break down the A11-A8 signals to address some devices. The A side of the 74LS139 at 4G is enabled by I/O. If A11 & A10 are low (C0xx), then the write line for the two 7489 16x4bit RAMs (used as color RAMs at 1B & 2B) are chosen. Note: there is no way for the CPU to READ these RAMs! If A11 is high and A10 is low (C8xx), then the A side of the 74LS139 at 6H is enabled. If A11 & A10 are high (CCxx), then the 6514 battery backed up CMOS SRAM at 1C is selected. If A9 & A8 are low, the A side of the 74LS139 at 6H will select (A2 needs to be high and A3 low in order for the PIA to be activated) the widget board PIA (6821) at IC2. If A9 & A8 are high, then the 8T97 at 3B can be enabled if A0 is low AND/OR the last signal needed by the 74LS133 at 5G to reset the watchdog is given.